This invention relates to a reconfigurable processor and a reconfigurable apparatus.
In recent years, a processor has been demanded to have not only performance of computing data being constantly input in real time at a high speed, but also high versatility to facilitate changing of an implemented logic.
For example, in a case of a processor used in a network security field, performance of computing communication data being constantly input in real time at a high speed, and versatility which enables frequent updating of an algorithm for detecting abnormalities of the communication data, or a pattern file have been required.
In a case of a processor used in a video processing field, performance of computing video data constantly input in real time at a high speed, and versatility of performing various processings for the video data by combining a plurality of operations such as encoding/decoding, down-conversion, copyright information addition, division, synthesis, and format conversion have been required.
However, the high versatility to facilitate changing of the implemented logic cannot be obtained by ASIC which includes a dedicated circuit. The high-speed computing processing performance of the real-time data cannot be obtained by a general-purpose processor.
As a processor to simultaneously realize the two performances, a processor called a reconfigurable processor (RP) has been developed and has been attracting attention. This processor is largely classified into three systems, that is, an AND-OR system, a look up table (LUT) system, and an ALU (Arithmetic Logical Unit) system.
The AND-OR system is a system which uses an AND-OR logic array as a logical element. According to this AND-OR system, high density of logics can be achieved because of small logical units (refer to U.S. Pat. No. 4,609,986).
The LUT system is a system which uses a LUT composed of a synchronous random access memory (SRAM) as a logical element. A high-level random logic is realized by prerecording a value of each input signal to the LUT (refer to U.S. Pat. No. 4,642,487).
The ALU system is a system which uses an ALU having functions of computing, retiming, and a memory predesignated as a logical element. It is called a dynamic reconfigurable processor (DRP). This computer system can change an implemented logic by one clock cycle, and has high versatility (refer to WO 02/095946).
The processor of the ALU system includes a reconfigurable circuit composed of a logical element having functions of computing, retiming, memory, and the like, and a bus for enabling free connection among the logical elements, and processes data through a pipeline system according to the connection among the logical elements. Further, an implemented logic of this reconfigurable circuit can be freely reconfigured by changing the connection among the logical elements. Accordingly, the processor of the computer system realizes high-speed processing performance and high versatility.
However, the processor of the ALU system performs data computing through the pipeline system, so when the implemented logic of the reconfigurable circuit is updated, data flowing through the circuit is destroyed, causing a problem of a loss of input data.
Thus, a system that changes the implemented logic of the reconfigurable circuit without losing the input data has been proposed. There have been proposed a system for changing two reconfigurable circuits, that is, currently used and spare reconfigurable circuits by a switch to realize the changing of the implemented logic without any data loss, a system for accumulating input data through an input buffer to change the implemented logic at a point when there is no more data left in the reconfigurable circuit, and the like (refer to “Studies on Uninterruptible Reconfiguration Method in Packet Transfer Processing” by Hidenori Kai and Hiroki Yamada, Society Conference of the Institute of Electronics, Information and Communication Engineers, B-6-150, Sep. 2003).